Design of quaternary logic gate using double pass-transistor logic with neuron MOS down literal circuit

Author

Park, Soo Jin ; Yoon, Byoung Hee ; Yoon, Kwang Sub ; Kim, Heung Soo

Author_Institution

Dept. of Electron. Eng., Inha Univ., Inchon, South Korea

fYear

2004

fDate

19-22 May 2004

Firstpage

198

Lastpage

203

Abstract

A multi-valued logic (MVL) pass gate is an important element in configuring multi-valued logic. Multiple logical levels, which are different from binary pass gates, are required to be discriminated in MVL pass gates. In this paper, we designed the quaternary MIN (QMIN)/negated MIN (QNMIN) gate, and the quaternary MAX (QMAX)/negated MAX (QNMAX) gate using double pass-transistor logic (DPL) with neuron MOS (vMOS) threshold gates. In addition, we designed quaternary truncated sum (QTS) and quaternary truncated difference (QTD) gates using vMOS down literal circuits (DLC). The DPL improved the gate speed without increasing the input capacitance. It has a symmetrical arrangement and double-transmission characteristics. The threshold gates are composed of vMOS DLC. The proposed gates obtain the signal value, to realize various multi threshold voltage circuits. In this paper, these circuits use a 3 V power supply voltage and the parameters of the 0.35 μm N-well 2-poly 4-metal CMOS technology. HSPICE simulation results are also presented.

Keywords

CMOS logic circuits; logic gates; multivalued logic circuits; threshold logic; 0.35 micron; 3 V; CMOS; DLC; DPL; MVL pass gate; QMAX/QNMAX logic gates; QMIN/QNMIN logic gates; double pass-transistor logic; multiple threshold voltages; multiply-valued logic; neuron MOS down literal circuit; quatemary MAX/negated MAX gate; quaternary MIN/negated MIN gate; quaternary logic gate; quaternary truncated difference gate; quaternary truncated sum gate; vMOS threshold gate; CMOS technology; Capacitance; Logic circuits; Logic design; Logic gates; Multivalued logic; Neurons; Page description languages; Power supplies; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Multiple-Valued Logic, 2004. Proceedings. 34th International Symposium on

ISSN

0195-623X

Print_ISBN

0-7695-2130-4

Type

conf

DOI

10.1109/ISMVL.2004.1319941

Filename

1319941