Design of fixed-point high-performance FFT processor

This paper, based on the complexity and hardware requirement of conventional FFT algorithms, analyses the architecture of radix-4 Single-Path Delay Feedback (SDF) in DIF and present an efficient FFT processor for real-time applications. A test bench is built up comparing Signal to Quantization Noise Ratio (SQNR) performances of the processors with a float-point model and fixed-point one. Several values of I/O word length and twiddle factor word length are implemented, to investigate the quantization effect of fixed-point arithmetic with limited precision derived from rounding or truncation errors, for enhancing the output performance. The simulation tests and an implementation of 1024-point FFT targeted on XC5VSX50T FPGA, show that the proposed FFT processor has a high computational frequency and hence suitable for usual OFDM wireless applications.