Microstrip equivalent parasitics modeling of RFIC interconnects

We experimentally demonstrate a modeling methodology for inductive parasitics of RFIC interconnects. The method exploits the equivalence between a microstrip line and the cross section of a multi metal layer CMOS fabrication process. The proposed model is applied on an oscillator fabricated in a standard 0.18 mum mixed mode CMOS process. We compare the experimental results of the phase noise of the oscillator so fabricated with the simulation results using the microstrip equivalent model for the interconnects. The simulation and experimental results match very closely.