Title :
A current-mode latch sense amplifier and a static power saving input buffer for low-power architecture
Author :
Kobayashi, T. ; Nogami, K. ; Shirotori, T. ; Fujimoto, Y. ; Watanabe, O.
Author_Institution :
Toshiba Corp., Kawasaki, Japan
Abstract :
Two circuit schemes for reducing power dissipation are proposed. The first is a current-mode latch sense amplifier that achieves power reduction without degradation of the access speed compared with conventional current-mirror sense amplifier operation. The other is a static power saving input buffer (SPSIB) for reducing static power. These circuits are applied to 512-kb high-speed SRAMs, and the efficiencies are simulated by SPICE simulations. The current-mode latch sense amplifier effectively reduces the power, and the SPSIB reduces current in the interface circuit.<>
Keywords :
CMOS integrated circuits; SRAM chips; VLSI; SPICE simulations; access speed; circuit schemes; current-mode latch sense amplifier; high-speed SRAMs; interface circuit; low-power architecture; power dissipation reduction; static power saving input buffer; Delay; Latches; MOSFET circuits; Operational amplifiers; Power amplifiers; Power dissipation; Pulse amplifiers; Semiconductor optical amplifiers; Timing; Very large scale integration;
Conference_Titel :
VLSI Circuits, 1992. Digest of Technical Papers., 1992 Symposium on
Conference_Location :
Seattle, WA, USA
Print_ISBN :
0-7803-0701-1
DOI :
10.1109/VLSIC.1992.229252
