A quick intelligent program architecture for 3 V-only NAND-EEPROMs

Author

Tanaka, T. ; Tanaka, Y. ; Nakamura, Hajime ; Oodaira, H. ; Aritome, S. ; Shirota, R. ; Masuoka, F.

Author_Institution

Toshiba Corp., Kawasaki, Japan

fYear

1992

fDate

4-6 June 1992

Firstpage

20

Lastpage

21

Abstract

A quick program/program verify architecture with an intelligent verify circuit for 3-V-only NAND-EEPROMs is described. The verify circuit, which is composed of two transistors, provides a simple, intelligent program algorithm for 3-V-only operation. The total programming time is reduced to 50%. By using intelligent verify circuits, the memory cells which require more time to reach the program state are automatically detected. Verify-read, the modification of program data, and data reload are performed simultaneously. The chip size penalty is estimated to be only 1% for a 16-Mb NAND-EEPROM.<>

Keywords

EPROM; MOS integrated circuits; NAND circuits; PLD programming; VLSI; 16 Mbit; 3 V; 3-V-only operation; NAND-EEPROMs; chip size penalty; data reload; intelligent verify circuit; memory cells; modification of program data; programming time; quick intelligent program architecture; verify read; Batteries; Circuits; Clocks; Flip-flops; Latches; Marketing and sales; Ultra large scale integration; Virtual manufacturing; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 1992. Digest of Technical Papers., 1992 Symposium on

Conference_Location

Seattle, WA, USA

Print_ISBN

0-7803-0701-1

Type

conf

DOI

10.1109/VLSIC.1992.229256

Filename

229256