Title :
A 100 MHz superscalar PA-RISC CPU/coprocessor chip
Author :
Yetter, J. ; Miller, B. ; Jaffe, W. ; Delano, E.
Author_Institution :
Hewlett-Packard Co., Fort Collins, CO, USA
Abstract :
A RISC CPU chip has been designed for 100-MHz operation. The chip combines a 32-b integer core and a full 64-b floating point coprocessor on a 1.43-cm*1.43-cm die. The chip is fabricated in a 0.8- mu m CMOS process with three layers of aluminum interconnect. It contains in excess of 850000 transistors. Many of the CPU circuits were adapted from an earlier CPU designed for 66 MHz in a 1- mu m-gate process. Careful characterization of that circuit combined with design shrinkage to 0.8 mu m yielded the desired performance. Other circuits were directly designed for 100-MHz operating frequency in the scaled process.<>
Keywords :
CMOS integrated circuits; VLSI; microprocessor chips; reduced instruction set computing; satellite computers; 0.8 micron; 1.43 cm; 100 MHz; 32 bit; 64 bit; CMOS; RISC CPU chip; characterization; design shrinkage; floating point coprocessor; integer core; operating frequency; scaled process; square die; superscalar/coprocessor chip; Arithmetic; Central Processing Unit; Clocks; Coprocessors; Delay; Logic circuits; Pipelines; Reduced instruction set computing; Semiconductor device measurement; System buses;
Conference_Titel :
VLSI Circuits, 1992. Digest of Technical Papers., 1992 Symposium on
Conference_Location :
Seattle, WA, USA
Print_ISBN :
0-7803-0701-1
DOI :
10.1109/VLSIC.1992.229260
