Title :
Using MORRPH in an industrial machine vision system
Author :
King, William E. ; Drayer, Thomas H. ; Conners, Richard W. ; Araman, Phil
Author_Institution :
Nova Technol., Charlotte, NC, USA
Abstract :
This paper describes the use of the MORRPH board (an FPGA-based CCM) in an industrial machine vision system. The system is designed to solve the color sorting problem in the furniture manufacturing industry. This entails classifying wooden samples (staves) into one of several predetermined color classes, so that all members of a particular class “match”. In this system, two MORRPH boards are used to perform the “early” processing, including: field-of-view operators, light-intensity monitoring, shading correction background extraction, color-quantization, gray-scale channel generation, and histogram generation. This functionality utilizes the following MORRPH board features: open support sockets are filled with various SRAMs depending on necessary requirements, functionality is time-multiplexed by reprogramming the FPGAs, one of three I/O Busses is used for high-bandwidth input of color camera data, the ISA Bus interface is used for low-bandwidth output of histogram data, user-programmable ports allow simple modification of operating parameters. The use of two MORRPH boards to perform the early processing provides almost 200 times the overall system throughput when compared to a system that used two 486-based PCs to perform the “early” processing
Keywords :
computer vision; field programmable gate arrays; industrial control; sorting; FPGA-based CCM; FPGAs; ISA Bus interface; MORRPH; color sorting problem; color-quantization; field-of-view operators; furniture manufacturing industry; gray-scale channel generation; histogram generation; industrial machine vision system; light-intensity monitoring; modular reprogrammable real time processing hardware; shading correction background extraction; wooden samples classification; Machine vision;
Conference_Titel :
FPGAs for Custom Computing Machines, 1996. Proceedings. IEEE Symposium on
Conference_Location :
Napa Valley, CA
Print_ISBN :
0-8186-7548-9
DOI :
10.1109/FPGA.1996.564738