Timing-driven decomposition of a fast barrel shifter

In state-of-the-art digital signal processing (DSP) and graphics applications, the shifter is an important module, consuming a significant amount of delay. This paper presents a new architectural optimization approach to synthesize a faster barrel shifter block, which can be very useful to reduce the delay of the design without significantly increasing the area. We have divided the problem of generating the shifter into two steps: timing-driven selection of multiple stages for merging, and the design of the merged stage. Techniques used in these two steps help to produce a faster implementation for the overall shifter block. Our experimental data shows that the shifter block generated by our algorithm is significantly faster (11.39% on average) than the corresponding block generated by a commercially available datapath synthesis tool.