DocumentCode
3267681
Title
A low power 12 b analog-to-digital converter with on-chip precision trimming
Author
deWit, M. ; Tan, K.S. ; Hester, R.K.
Author_Institution
Texas Instrum., Dallas, TX, USA
fYear
1992
fDate
4-6 June 1992
Firstpage
100
Lastpage
101
Abstract
The design and performance of a 12 b charge redistribution ADC is described. The architecture is chosen to minimize conversion time and power dissipation. Die area is minimized by a modified self-calibration algorithm and nonvolatile memory based on polysilicon fuses. The ADC is fabricated in a linear 1 mu m CMOS process. The die area, including the 12 b parallel digital interface is 15 kmil/sup 2/. The power dissipation is under 15 mW, making the energy per conversion only 45 nJ.<>
Keywords
CMOS integrated circuits; analogue-digital conversion; 1 micron; 12 bit; 15 mW; 45 nJ; CMOS process; analog-to-digital converter; architecture; charge redistribution ADC; conversion time; die area; energy per conversion; nonvolatile memory; on-chip precision trimming; polysilicon fuses; power dissipation; self-calibration algorithm; Analog-digital conversion; Calibration; Capacitors; Circuits; Error correction; Fuses; Linearity; Nonvolatile memory; Power dissipation; Production facilities;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 1992. Digest of Technical Papers., 1992 Symposium on
Conference_Location
Seattle, WA, USA
Print_ISBN
0-7803-0701-1
Type
conf
DOI
10.1109/VLSIC.1992.229272
Filename
229272
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