500 Mbyte/sec data-rate 512 Kbits*9 DRAM using a novel I/O interface

Author

Kushiyama, N. ; Ohshima, S. ; Stark, D. ; Sakurai, K. ; Takase, S. ; Furuyuma, T. ; Barth, B. ; Dillon, J. ; Gasbarro, J. ; Griffin, M. ; Horowitz, M. ; Lee, V. ; Lee, W. ; Leung, W.

Author_Institution

Toshiba Corp., Kawasaki, Japan

fYear

1992

fDate

4-6 June 1992

Firstpage

66

Lastpage

67

Abstract

A novel 512-kb*9 DRAM with a 500-Mbyte/s data transfer rate has been designed. This high data-rate has been achieved by coupling a very high internal column bandwidth DRAM core with a very high internal column bandwidth, and coupling this core with a block oriented, small-swing, synchronous interface that uses skew canceling clocks. The DRAM has a 1-kbyte*2 line sense amplifier cache. This DRAM is assembled in a 32-pin vertical surface mount type plastic package.<>

Keywords

CMOS integrated circuits; DRAM chips; surface mount technology; 4608 Kbit; 500 Mbyte/s; DRAM; I/O interface; data transfer rate; dynamic RAM; internal column bandwidth; plastic package; sense amplifier cache; skew canceling clocks; surface mount type; synchronous interface; vertical SMD package; Bandwidth; Clocks; Content addressable storage; Digital systems; Graphics; Logic; Microelectronics; Noise reduction; Random access memory; Signal generators;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 1992. Digest of Technical Papers., 1992 Symposium on

Conference_Location

Seattle, WA, USA

Print_ISBN

0-7803-0701-1

Type

conf

DOI

10.1109/VLSIC.1992.229280

Filename

229280