A 9 Gbit/s bandwidth multiplexer/demultiplexer CMOS chip

Author

Dunlop, A.E. ; Gabara, T.J. ; Fischer, W.C.

Author_Institution

AT&T Bell Lab., Murray Hill, NJ, USA

fYear

1992

fDate

4-6 June 1992

Firstpage

68

Lastpage

69

Abstract

A 622-MHz 28:7 multiplexer/demultiplexer (MUX/DEMUX) 0.9- mu m CMOS chip has been fabricated and tested. All inputs/outputs (I/O) communicate using 100 K ECL logic levels and are single-ended. The chip is packaged in a metal QFP (quad flat pack) package and generates less than 80 mV of ground noise when all outputs switch simultaneously. The total power dissipation is 2.5 W. The device has controlled loop-back paths for system diagnostic purposes. Tests show that the chip operates at more than 740 MHz.<>

Keywords

CMOS integrated circuits; demultiplexing equipment; digital communication systems; emitter-coupled logic; integrated logic circuits; multiplexing equipment; optical communication equipment; 0.9 micron; 2.5 W; 622 MHz; 740 MHz; 9 Gbit/s; CMOS chip; ECL logic levels; controlled loop-back paths; demultiplexer; metal QFP; multiplexer; optical fibre links; package; power dissipation; quad flat pack; system diagnostic; Bandwidth; CMOS logic circuits; Control systems; Electronics packaging; Logic devices; Multiplexing; Noise generators; Power dissipation; Switches; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 1992. Digest of Technical Papers., 1992 Symposium on

Conference_Location

Seattle, WA, USA

Print_ISBN

0-7803-0701-1

Type

conf

DOI

10.1109/VLSIC.1992.229281

Filename

229281