Grid-based wire resource estimation for the physical synthesis

Not only the wire delay exceeds the cell delay, but also the wire area also exceeds the cell area in deep submicron CMOS design. To ensure the design is mutable, the limited wire resource should be considered in the synthesis stage. In this paper, the grid-based wire estimation method used in the synthesis stage is presented. With this method, the required wire resource is estimated in the synthesis stage, the suitable circuit structure can be chosen to make the synthesized netlists routable.