A 1.28 Gbps 16*16 CMOS chip set for an output-buffer ATM switch

Author

Sugaya, N. ; Nagano, H. ; Morita, T. ; Kawanago, S. ; Kuriki, R. ; Sakamoto, Makoto ; Suzuki, T.

Author_Institution

NEC Corp., Kanagawa, Japan

fYear

1992

fDate

4-6 June 1992

Firstpage

76

Lastpage

77

Abstract

A CMOS chip set for a 1.28-Gb/s 16*16 output buffer ATM switch has been developed. By operating at 160 MHz with 8-b parallel input/output, a line speed of 1.28 Gb/s is achieved. 20.5-Gb/s (1.28 Gb/s*16) time division multiplexing has been realized by the introduction of a time multiplexing serial to parallel converter (TMSPC) that consists of flip-flops and 2-1 selectors in a matrix formation. Two clock drivers are used in a one phase scheme with a minimum of propagation delay. ECL-compatible I/O buffers have been used to handle high-speed signals. All chips are developed using 0.8- mu m double-metal CMOS technology.<>

Keywords

CMOS integrated circuits; asynchronous transfer mode; buffer storage; digital integrated circuits; electronic switching systems; integrated memory circuits; multiplexing equipment; 0.8 micron; 1.28 Gbit/s; 160 MHz; 20.5 Gbit/s; CMOS chip set; ECL-compatible I/O buffers; clock drivers; double-metal CMOS technology; flip-flops; matrix formation; monolithic IC; one phase scheme; output-buffer ATM switch; selectors; serial to parallel converter; time division multiplexing; Asynchronous transfer mode; CMOS technology; Clocks; Communication switching; Flip-flops; Matrix converters; National electric code; Routing; Switches; Time division multiplexing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 1992. Digest of Technical Papers., 1992 Symposium on

Conference_Location

Seattle, WA, USA

Print_ISBN

0-7803-0701-1

Type

conf

DOI

10.1109/VLSIC.1992.229285

Filename

229285