Title :
A dual PLL based multi frequency clock distribution scheme
Author :
Thaik, A. ; Nguyen, H.N.
Author_Institution :
Mips Computer Systems Inc., Sunnyvale, CA, USA
Abstract :
A clock generation scheme using two loosely coupled phase locked loops is presented. Each loop produces several clocks at different frequencies based on a single input clock. To minimize clock skew, a pipelined clock distribution structure is employed where clocks are resynchronized over multiple cycles en route to their destination. For low power applications, the design allows software to initiate a cycle-down mode, which causes all clocks to simultaneously divide down to lower frequencies by a programmable amount.<>
Keywords :
clocks; phase-locked loops; synchronisation; timing circuits; clock distribution scheme; clock generation scheme; cycle-down mode; dual PLL; low power applications; multifrequency clock; phase locked loops; pipelined clock distribution structure; Application software; Circuits; Clocks; Delay lines; Distributed computing; Frequency conversion; Frequency synchronization; Phase locked loops; Switches; Voltage-controlled oscillators;
Conference_Titel :
VLSI Circuits, 1992. Digest of Technical Papers., 1992 Symposium on
Conference_Location :
Seattle, WA, USA
Print_ISBN :
0-7803-0701-1
DOI :
10.1109/VLSIC.1992.229288
