DocumentCode
3267946
Title
A 0.6 mu m CMOS SOG with a 5 V/3.3 V interfaces
Author
Ohkawa, M. ; Takahashi, T. ; Yamagishi, M. ; Sonobe, Y. ; Ejima, N.
Author_Institution
Hitachi Ltd., Tokyo, Japan
fYear
1992
fDate
4-6 June 1992
Firstpage
88
Lastpage
89
Abstract
A 510-kG CMOS sea-of-gates (SOG) was experimentally developed using 0.6- mu m triple-metal-layer process technology and a 5-V/3.3-V interface. High-speed ASICs for high-performance processor systems supporting both TTL level and LVTTL level interfaces were developed. The 5-V/3.3-V interface concept employs a CMOS buffer on p-substrate, to choose an output high level of either 3.3 V or 5 V. The typical delay times of the internal gate and output buffer are 0.2 ns and 1.3 ns, respectively.<>
Keywords
CMOS integrated circuits; application specific integrated circuits; logic arrays; 0.2 ns; 0.6 micron; 1.3 ns; 3.3 V; 5 V; ASICs; CMOS SOG; CMOS buffer; LVTTL level interfaces; TTL level; high speed ASIC; p-substrate; sea-of-gates; triple-metal-layer process; CMOS logic circuits; CMOS process; CMOS technology; Circuit simulation; Delay effects; Delay systems; Large scale integration; Logic testing; Voltage; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 1992. Digest of Technical Papers., 1992 Symposium on
Conference_Location
Seattle, WA, USA
Print_ISBN
0-7803-0701-1
Type
conf
DOI
10.1109/VLSIC.1992.229290
Filename
229290
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