Highly reliable process insensitive 3.3 V-5 V interface circuit

Author

Wada, Y. ; Gotoh, J. ; Takakura, H. ; Iida, Tomoharu ; Noguchi, T.

Author_Institution

Toshiba Corp., Kawasaki, Japan

fYear

1992

fDate

4-6 June 1992

Firstpage

90

Lastpage

91

Abstract

By adopting a new process-insensitive output circuit, with a depression-type transistor and a new DC current free input circuit, a highly reliable 3.3-V-5-V interface circuit has been developed. Using a separated input-output structure, the circuit achieves a wide operating voltage range of 2.7 V to 3.6 V and a wide process margin. A reliable n-p-n lateral bipolar device yields a high ESD failure threshold. The circuit is fabricated by means of a 0.6- mu m standard CMOS process without multioxide.<>

Keywords

CMOS integrated circuits; circuit reliability; convertors; digital integrated circuits; electrostatic discharge; transistor-transistor logic; 0.6 micron; 2.7 to 3.6 V; 3.3 V; 5 V; CMOS process; DC current free input circuit; LVTTL level; TTL level; depression-type transistor; high ESD failure threshold; interface circuit; n-p-n lateral bipolar device; process-insensitive output circuit; separated input-output structure; voltage convertor; Breakdown voltage; Circuit synthesis; Degradation; Electrostatic discharge; Hot carriers; Leakage current; MOSFETs; Reliability engineering; Semiconductor device reliability; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 1992. Digest of Technical Papers., 1992 Symposium on

Conference_Location

Seattle, WA, USA

Print_ISBN

0-7803-0701-1

Type

conf

DOI

10.1109/VLSIC.1992.229292

Filename

229292