Design of low power multimode time-shared filters

This paper proposes a new class of time-shared filtering architectures targeted at low power multimode portable wireless applications. The proposed structures exploit the increased cycle period available in fast filter algorithm based parallel processing structures to operate at a lower supply voltage, thereby reducing the power consumption. Further power reductions are obtained due to the reduced number of multiplications in fast filter algorithms. The paper also presents a novel power consumption model for various time-shared filter architectures in a voltage scaling regime. The proposed model can be used to investigate the impact of varying the throughput, filter architecture, filter lengths, and parallelism on the power consumption.