A cascadable ASIC prototype for real time time-frequency analysis

Wide-band non stationary digital signals are extensively used by modern telecomunications applications. Analyzing those signals in real time is a complex task as we need a joint analysis in time and frequency which is called a time-frequency representation (TFR). As far as we know, there is currently no dedicated ASIC solution for TFR, as the usual approaches are computationally too intensive or do not meet resolution requirements both in time and frequency. In a previous paper we proposed an alternative architecture using a modulation/filtering/decimation/interleaving approach called F-TFR. In this paper, we present a cascadable prototype used to validate this architecture.