PLD integrates dedicated high-speed data buffering, complex state machine, and fast decode array

Many designs contain both complex synchronous logic and fast asynchronous logic which must be integrated in Programmable Logic Devices (PLDs). For example, some systems have a need for a specialized memory controller, usually a big state machine, as well as a need to decode high speed combinatorial signals such as chip selects, RAS and CAS, bank switching signals, etc. If the PLD is to be synchronized with the rest of the system, additional flip-flops will also be needed to buffer input signals. Implementing such designs in standard PLDs can be difficult since a PLD must meet the conflicting demands of control logic complexity and high-speed data buffering/decoding. In situations like this, the designer may wish to try a unique solution like the MAPL244 PLD from National Semiconductor. This paper utilizes a multiport buffer memory controller application to illustrate how to take advantage of the MAPL244´s integrated state machine/control logic array, fast decode array, and high speed input data buffers