Title :
A high PSRR capacitor-less on — Chip low dropout voltage regulator
Author :
Abbasi, Mohammad Usaid ; Bagnall, Darren ; Bn, Vishwas
Author_Institution :
Dept. of Electron. & Comput. Sci., Univ. of Southampton, Southampton, UK
Abstract :
A design of a high PSRR capacitor-less low dropout voltage regulator (LDO) is presented. This circuit is stable for full load current range from 0 to 100mA. A mid frequency zero has been introduced to stabilize the loop. The PSRR achieved was -71.258dB at 130kHz, and more than -40dB upto 650.750kHz. The LDO is capable of generating fixed 1V from a supply of 3.0V which on discharging goes to 1.5V. The LDO has been implemented in 0.18μm generic CMOS technology. Simulation result showed that the line regulation achieved was 370μV/V and load regulation was just 0.01173%/mA.
Keywords :
CMOS analogue integrated circuits; circuit stability; integrated circuit design; integrated circuit modelling; load regulation; voltage regulators; LDO simulation; circuit stability; current 0 mA to 100 mA; discharging; frequency 130 kHz to 650.750 kHz; generic CMOS technology; high PSRR capacitorless on-chip low dropout voltage regulator design; line regulation; load regulation; midfrequency zero; size 0.18 mum; voltage 3.0 V; Batteries; Capacitance; Capacitors; Regulators; Transient response; Transistors; Voltage control; Analog circuit design; LDO; capacitor-less LDO; high PSRR; line regulation; load regulation;
Conference_Titel :
Intelligent Systems and Informatics (SISY), 2010 8th International Symposium on
Conference_Location :
Subotica
Print_ISBN :
978-1-4244-7394-6
DOI :
10.1109/SISY.2010.5647405
