Title :
Challenges to the low power technology for future system LSIs
Author_Institution :
NEC Corp., Kawasaki, Japan
Abstract :
This paper discusses low power technology for future system LSIs. At present, no simple way has been found to reduce the power dissipation to meet the requirements. A wide range of technology layers from architectures to materials should be considered, and application oriented solutions should be sought.
Keywords :
CMOS integrated circuits; large scale integration; low-power electronics; CMOS; LSI architectures; LSI materials; low power technology; power dissipation; system LSI; CMOS technology; Circuit synthesis; Circuit testing; Frequency; Large scale integration; Leakage current; Plastics; Power dissipation; Signal design; Signal synthesis;
Conference_Titel :
Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on
Print_ISBN :
0-7803-8511-X
DOI :
10.1109/ICSICT.2004.1435240
