Realization of high data rate DUC based on FPGA

This paper discusses the issues on “how to save multiplier resource” and “how to cope with high data rate”, when implementing Digital Up Converter (DUC) with Field Programmable Gate Array (FPGA). A novel implementation structure of poly-phase interpolation filter is proposed, which could reduce the consumption of multiplier by half. Parallel processing is adopted in designing Numerical Controlled Oscillator (NCO), which could generate high data rate LO required. By following these methods, a DUC module is designed for certain radar IF echo simulator, which could generate digital IF signal with data rate up to 1.2Gsps.