DocumentCode
3268617
Title
A complete BIST scheme for ADC linearity testing
Author
Guanglin, Wu ; Ming, Ling ; Jin, Rao ; Longxing, Shi
Author_Institution
Nat. ASIC Syst. Eng. Center, Southeast Univ., Nanjing, China
Volume
3
fYear
2004
fDate
18-21 Oct. 2004
Firstpage
2051
Abstract
In this paper, we presented algorithms for testing gain error, offset error, differential nonlinearity (DNL) and integral nonlinearity (INL) of analog-to-digital converters (ADC), and proposed an easily integrated built-in self-test (BIST) scheme on chip, which has been designed using Chartered 0.35 μm technology. The experimental results show that the proposed BIST scheme has low area overhead, low test cost and high test accuracy.
Keywords
analogue-digital conversion; built-in self test; integrated circuit testing; mixed analogue-digital integrated circuits; 0.35 micron; ADC linearity testing; BIST scheme; DNL; INL; area overhead; differential nonlinearity; gain error; integral nonlinearity; mixed-signal IC testing; offset error; test accuracy; test cost; Analog-digital conversion; Built-in self-test; Circuit testing; Digital signal processing; Digital-analog conversion; Integrated circuit technology; Integrated circuit testing; Linearity; Mixed analog digital integrated circuits; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on
Print_ISBN
0-7803-8511-X
Type
conf
DOI
10.1109/ICSICT.2004.1435246
Filename
1435246
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