On estimation and optimization of leakage power in CMOS multipliers

The proliferation of high performance processors has been enabled by shrinking feature sizes in CMOS technology. This reduction in feature sizes enables designers to scale down the supply and threshold voltages accordingly. Although reduced threshold voltage improves the speed of the devices, it also leads to increased static power dissipation. In this paper, the static leakage power characteristics of CMOS multiplier circuits are analyzed as they are the most expensive and slow units in the datapath of a microprocessor. Each of the multipliers (carry-save, bit-array, and Wallace) is implemented at two different technology sizes (65 nm and 45 nm) realized using three different full adders (10 Transistor (10 T) adder, Static energy recovery full adder and Mirror adders). Among the three multipliers, the carry-save multiplier consumed maximum leakage current at both 65 nm and 45 nm technology nodes. The Wallace tree multiplier dissipated minimum leakage current owing to its structure. In order to reduce the leakage current in each of the multiplier circuits, a heuristic approach is proposed to incorporate hybrid adder modules in the final stage of multiplication that forms the critical delay path and also a high static leakage current zone. Placing Mirror adder and 10 T adders alternatively in the final stage yielded better leakage power characteristics.