Advanced microarchitecture simulator for design, verification and synthesis

Accurate functional and timing verification of microarchitecture designs requires detailed models at register-transfer level (RTL). The complexity in microarchitecture designs is foreseeable with the introduction of multi-core processor architectures. Simulations at such a detailed level are computation intensive. A new microarchitecture simulator - OSU AbaKus - is developed to address the simulation speed together with accurate functional and timing design verification. The modular approach of the simulator, that is in close correlation with the digital hardware design enables to add and modify designs easily. A detailed superscalar architecture is tested and the throughput of the simulators is compared with SimpleScalar sim-outorder.