Title :
64-bit pipeline conditional carry adder with MTCMOS TSPC logic
Author_Institution :
Far East Univ. Hsin-Shih, Tainan
Abstract :
In this study, a 64-bit 8-stage pipeline conditional- carry adder (CCA) with the Multi-Threshold voltage CMOS (MTCMOS) TSPC logic for power-aware applications was designed and verified. The 64-bit pipeline CCA needs 4 cycles only. Transistors on critical paths use a low threshold voltage to increase the operation speed. Other transistors use a normal threshold voltage to save power. Compare with single normal threshold voltage TSPC schemes, the proposed pipeline scheme has a higher operation frequency and better power-frequency ratio. Furthermore, the circuit style of proposed multiplexer can be extended on high-speed FPGA or pass-transistor logic (PTL). The simulations show that the 64-bit CCA with MTCMOS TSPC can be operated on 2.4GHz and its power / maximal frequency ratio is 43.9 muW/MHz.
Keywords :
CMOS digital integrated circuits; adders; carry logic; field programmable gate arrays; multiplexing equipment; probabilistic logic; transistor-transistor logic; 64-bit pipeline conditional carry adder; MTCMOS TSPC logic; high-speed FPGA; multiplexer; multithreshold voltage CMOS; normal threshold voltage; pass-transistor logic; transistors; true-single phase clocking logic; Adders; CMOS logic circuits; Circuit simulation; Field programmable gate arrays; Frequency; Logic circuits; Logic design; Multiplexing; Pipelines; Threshold voltage; 64-bit; MTCMOS; TSPC; adder; conditional carry; conditional sum; multiplexer;
Conference_Titel :
Circuits and Systems, 2007. MWSCAS 2007. 50th Midwest Symposium on
Conference_Location :
Montreal, Que.
Print_ISBN :
978-1-4244-1175-7
Electronic_ISBN :
1548-3746
DOI :
10.1109/MWSCAS.2007.4488712
