A test implementation approach for VLSI testable design

A test implementation approach for VLSI testable design, with functional testing interacting on structural testing, is presented. Compared with a simple test combination combining functional testing and structural testing, the test implementation approach can reach a precise calculation of the total fault coverage to achieve a reliable test evaluation with fewer redundant test vectors to reduce the time of testing. The features of the test implementation approach are described. A constructive framework of the approach as well as a precise calculation equation for final fault coverage is proposed. Then, the approach is applied in an MCU design.