Title :
A 3.3 V-only 16 Mb flash memory with row-decoding scheme
Author :
Atsumi, S. ; Umezawa, A. ; Kuriyama, M. ; Banba, H. ; Ohtsuka, N. ; Tomita, N. ; Iyama, Y. ; Miyaba, T. ; Sudoh, R. ; Kamiya, E. ; Tanimoto, Masahiro ; Hiura, Y. ; Araki, Yuichi ; Sakagami, E. ; Arai, Nobuyuki ; Mori, Shinsuke
Author_Institution :
Semicond. Device Eng. Lab., Toshiba Corp., Kawasaki, Japan
Abstract :
A 3.3 V only 16 M flash memory with a row decoding scheme is fabricated in 0.4 /spl mu/m double-well double-metal CMOS. Negative-gate-biased erase enables 3.3 V-only operation, and a double-word-line structure with second aluminum minimizes word-line delay. Row redundancy with self-convergence improves yield. Quasi-differential sensing with address transition detection gives fast random access.
Keywords :
CMOS memory circuits; EPROM; decoding; 0.4 micron; 16 Mbit; 3.3 V; Al; address transition detection; delay; double-well double-metal CMOS process; double-word-line structure; flash memory; negative-gate-biased erase; quasi-differential sensing; random access; redundancy; row decoding; self-convergence; yield; Charge pumps; Circuits; Decoding; Flash memory; Laboratories; Microelectronics; Redundancy; Semiconductor devices; Stress; Threshold voltage;
Conference_Titel :
Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC., 1996 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-3136-2
DOI :
10.1109/ISSCC.1996.488506
