A 55 ns 0.35 /spl mu/m 5 V-only 16 M flash memory with deep-power-down

Author

Venkatesh, B. ; Chung, Ming-Hsien ; Govindachar, S. ; Santurkar, V. ; Bill, C. ; Gutala, R. ; Zhou, Dizhi ; Yu, Jinpeng ; Van Buskirk, M. ; Kawamura, Sadao ; Kurihara, Keiichirou ; Kawashima, Hitoshi ; Watanabe, Hiromi

Author_Institution

Adv. Micro Devices Inc., Sunnyvale, CA, USA

fYear

1996

fDate

10-10 Feb. 1996

Firstpage

44

Lastpage

45

Abstract

An embedded 5 V only 16 M flash memory has an on-chip state machine that generates embedded program and erase algorithms, eliminating system execution of these operations. The system issues a series of commands decoded by the state machine for on-chip execution. It is a /spl times/8 part with a read/busy pin to indicate to the system if the part is in an embedded mode, and a RESETB pin to terminate any operation being executed by the state machine and reset the part to the read mode. Erase is by applying a negative voltage to the control gate of the array and a positive voltage VS to the sector array source.

Keywords

CMOS memory circuits; EPROM; 0.35 micron; 16 Mbit; 5 V; 55 ns; RESETB pin; deep-power-down; embedded algorithms; flash memory; on-chip state machine; read/busy pin; CMOS technology; Counting circuits; Decoding; Flash memory; Logic circuits; Logic programming; Pumps; Resumes; Signal generators; User interfaces;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC., 1996 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-3136-2

Type

conf

DOI

10.1109/ISSCC.1996.488507

Filename

488507