Title :
A 0.9-V 10-bit 100-MSample/s pipelined ADC using switched-RC and opamp sharing techniques
Author :
Hashemi, Sedigheh ; Shoaei, Omid
Author_Institution :
Univ. of Tehran, Tehran
Abstract :
This paper presents a very low-voltage low-power pipelined ADC with 0.9-V supply voltage in a 90 nm CMOS process. A novel switched-RC sampling MDAC is used to obtain high linearity under low-voltage condition without significant degradation in speed. With the aim of achieving low-voltage and low-power operation, a non-uniform per-stage resolution which increases the resolution of the back-end stages at the architectural level, and an opamp sharing technique at the circuit level are used. According to HSPICE simulation results, the 10-bit 100 MSample/s ADC with 1-Vp.p,diff input signal in a 90 nm CMOS process and 0.9-V supply voltage achieves an SNDR of 58 dB and consumes 17.6 mW power.
Keywords :
CMOS integrated circuits; analogue-digital conversion; low-power electronics; operational amplifiers; CMOS process; low-power pipelined ADC; low-voltage condition; opamp sharing technique; size 90 nm; switched-RC sampling MDAC; voltage 0.9 V; Analog circuits; CMOS process; Circuit simulation; Clocks; Linearity; Low voltage; MOS devices; Sampling methods; Switches; Switching circuits;
Conference_Titel :
Circuits and Systems, 2007. MWSCAS 2007. 50th Midwest Symposium on
Conference_Location :
Montreal, Que.
Print_ISBN :
978-1-4244-1175-7
Electronic_ISBN :
1548-3746
DOI :
10.1109/MWSCAS.2007.4488720