• DocumentCode
    3269014
  • Title

    New energy recovery CMOS XNOR/XOR gates

  • Author

    Xu, Y. ; Srivastava, A.

  • Author_Institution
    Louisiana State Univ., Baton Rouge
  • fYear
    2007
  • fDate
    5-8 Aug. 2007
  • Firstpage
    948
  • Lastpage
    951
  • Abstract
    In this paper, new energy recovery CMOS XNOR/XOR gates have been proposed. These circuits have been simulated using Cadence/Spectre along with three other XNOR/XOR gates. The results show that the new CMOS XNOR/XOR gates consume 30% less power than in the clocked adiabatic logic (CAL). Experimental results on new energy recovery CMOS XNOR/XOR gates fabricated in standard 0.5 mum n-well CMOS process follow the simulation results.
  • Keywords
    CMOS logic circuits; logic gates; low-power electronics; Cadence-Spectre; clocked adiabatic logic; energy recovery CMOS XNOR-XOR gates; size 5 nm; CMOS logic circuits; Clocks; Cooling; Energy loss; Inverters; Logic devices; Power dissipation; Power supplies; Switches; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2007. MWSCAS 2007. 50th Midwest Symposium on
  • Conference_Location
    Montreal, Que.
  • ISSN
    1548-3746
  • Print_ISBN
    978-1-4244-1175-7
  • Electronic_ISBN
    1548-3746
  • Type

    conf

  • DOI
    10.1109/MWSCAS.2007.4488723
  • Filename
    4488723
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3269014