Leakage aware full adder cell

In deep submicron technologies, static power dominates total power consumption. Introducing leakage awareness to the basic building blocks of parallel architectures is a decisive factor to cut off the leakage currents when appropriate. In this paper, a leakage awareness technique is applied to the full adder cell (FA) of an array multiplier. This reduces the leakage current of the FA cell by approximately 20%, assuming that the multiplier is continuously running and that the input bits have equal probabilities of occurrence.