Title :
Probabilistic leakage power estimation of Partially-Depleted Silicon-On-Insulator (SOI) gates
Author :
Kim, Kyung Ki ; Kim, Yong-Bin
Author_Institution :
Northeastern Univ., Boston
Abstract :
This paper presents a novel probability based analysis for leakage power estimation of partially-depleted silicon-on-insulator (PD-SOI) circuits. The proposed leakage power estimation algorithms is implemented in C language, and the proposed methodology is tested by ISCAS85 benchmark circuits designed in 100 nm SOI technology. The results show that the error is within 4% compared with Hspice Monte Carlo simulation results.
Keywords :
C language; electronic engineering computing; estimation theory; leakage currents; logic design; logic gates; probability; silicon-on-insulator; C language; Hspice Monte Carlo simulation; ISCAS85 benchmark circuit; SOI gates; leakage power estimation; partially-depleted silicon-on-insulator circuit; probability analysis; size 100 nm; Benchmark testing; CMOS technology; Circuit testing; History; Leakage current; Semiconductor device modeling; Silicon on insulator technology; Subthreshold current; Threshold voltage; Tunneling;
Conference_Titel :
Circuits and Systems, 2007. MWSCAS 2007. 50th Midwest Symposium on
Conference_Location :
Montreal, Que.
Print_ISBN :
978-1-4244-1175-7
Electronic_ISBN :
1548-3746
DOI :
10.1109/MWSCAS.2007.4488728
