Parasitic-aware physical design optimization of deep sub-micron analog circuits

Performance, versatility, portability and reliability are common goals of robust designs. In deep sub-micron technologies, these goals often contain contradicting objectives only revealed at the physical design level. Design objectives often cannot be effectively satisfied without exploring detailed trade-offs. Well-performing schematic designs can hence only be realized if followed-through with a quality-based physical design flow. We present a performance-driven physical design algorithm to optimize custom analog circuits containing guard bands in mixed-signal environment. Parasitic effects are minimized under symmetry, matching and displacement constraints while preserving the customized layout topology.