The Research and Application of a Specific Instruction Processor for SMS4

SMS4 is a block cipher used in the Chinese National Standard for Wired Authentication and Privacy Infrastructure (WAPI). Like other cryptosystems, the SMS4 contains data-intensive computation, whose throughput makes a substantial contribution to the overall system performance. Design and implementation of the SMS4 cryptosystem to meet the real-time requirements of applications are challenge problems, especially for embedded network systems with limited computation resources. In this work, we present a systematic design approach of application-specific instruction-set processor (ASIP) for the SMS4 cryptographic algorithm, which exploits and compromises between the flexibility of software execution and the performance of the application-specific integrated circuit (ASIC) based implementation of the SMS4 cryptosystem. We identify and perform a design space exploration of the custom instructions found for the SMS4 algorithm, and extend the instruction set architecture (ISA) of a standard 32-bit RISC processor to accommodate them. We employ the Electronic System Level (ESL) methodology in the development of the proposed ASIP using the Xilinx Virtex5 LX110T FPGA platform. Results show that compared to the original RISC ISA, our ASIP for SMS4 achieves 2.93 times performance improvement and 52.4% less program memory utilization, with only 28.2% more resource required.