DocumentCode
3269446
Title
Predicting processor performance with a machine learnt model
Author
Beg, Azam
Author_Institution
UAE Univ., Al-Ain
fYear
2007
fDate
5-8 Aug. 2007
Firstpage
1098
Lastpage
1101
Abstract
Architectural simulators are traditionally used to study the design trade-offs for processor systems. The simulators are implemented in a high-level programming language or a hardware descriptive language, and are used to estimate the system performance prior to the hardware implementation. The simulations, however, may need to run for long periods of time for even a small set of design variations. In this paper, we propose a machine learnt (neural network/NN) model for estimating the execution performance of a superscalar processor. Multiple runs for the model are finished in less than a few milliseconds as compared to days or weeks required for simulation-based methods. The model is able to predict the execution throughput of a processor system with over 85% accuracy when tested with six SPEC2000 CPU integer benchmarks. The proposed model has possible applications in computer architecture research and teaching.
Keywords
hardware description languages; high level languages; learning (artificial intelligence); neural nets; hardware descriptive language; high-level programming language; machine learnt model; processor systems; Benchmark testing; Computational modeling; Computer languages; Hardware; Neural networks; Predictive models; Process design; System performance; System testing; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2007. MWSCAS 2007. 50th Midwest Symposium on
Conference_Location
Montreal, Que.
ISSN
1548-3746
Print_ISBN
978-1-4244-1175-7
Electronic_ISBN
1548-3746
Type
conf
DOI
10.1109/MWSCAS.2007.4488749
Filename
4488749
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