Standard cell based pseudo-random clock generator for statistical random sampling of digital signals

A statistical random sampling technique has recently emerged as an elegant design-time efficient technique to address many timing issues of on-chip signals. To obtain reliable measurement results, it requires uniformly distributed sampling edges within the interval defined by the periodic cycles of the signal under measurement. This paper analyzes the characteristics of a random sampling clock relative to the signal under measurement and provides design rules for synthesis of pseudo-random sampling clocks. The proposed circuit provides a way to mix a range of frequencies in a pseudo-random fashion to produce uniformly distributed edges for random sampling, which yields measurement accuracy very close to that of true random sampling. A practical circuit design technique of pseudo-random clock generation is proposed based on a standard cell approach. This allows on-chip integration of a random clock generator while keeping the overall system design-time efficient and portable across varying technologies. The proposed designs are targeted to IBM Cu-08 standard cell libraries and provide a measurement resolution of 1 ps.