Data strobe timing of DDR2 using a statistical random sampling technique

This paper presents a new way to tackle critical bus cycle timing issues related to DDR/DDR2 bus operations using a statistical random sampling technique. The technique allows a pure standard cell based design which is inherently area, power and design time efficient compared to existing solutions proposed in the literature. The proposed design employs a statistical random sampling technique to measure and correct the duty cycle of a clock to produce source synchronous signals and to adjust the phase of the incoming strobe to correctly capture data. The proposed circuits are used to interface Samsung K4T51163QB_D5 DDR2 chips to a massively parallel processing logic ASIC chip, targeted to IBM Cu-08 90 nm technology. The proposed design is a fully digital solution based on standard cell components and does not require any custom designed component. This makes it extremely design time efficient and portable across most ASIC and FPGA technologies.