Digital-phase aligner macro for clock tree compensation with 70 ps jitter

This paper describes a digital phase aligner (DPA) that can be used to decrease the chip-to-chip clock skew caused by process and temperature variations of the on-chip clock trees in a multiple-chip synchronous system with multiple clock domains. This method adjusts the delay of a variable-delay line to align an output of the clock tree to the clock input of a chip. Delay is added to make the clock tree latency an integral number of cycles. The goal was to design a delay-locked loop over a 8-25 ns cycle time with low jitter, allow multiple uses per ASIC, have the ability to start and stop the external clock without a long period of initialization and be fully testable by level-sensitive scan design (LSSD).