• DocumentCode
    3269553
  • Title

    Flow-through latch and edge-triggered flip-flop hybrid elements

  • Author

    Partovi, H. ; Burd, R. ; Salim, U. ; Weber, F. ; DiGregorio, L. ; Draper, D.

  • Author_Institution
    NexGen, Milpitas, CA, USA
  • fYear
    1996
  • fDate
    10-10 Feb. 1996
  • Firstpage
    138
  • Lastpage
    139
  • Abstract
    This paper describes a hybrid latch-flipflop (HLFF) timing methodology aimed at a substantial reduction in latch latency and clock load. A common principle is employed to derive consistent latching structures for static logic, dynamic domino and self-resetting logic.
  • Keywords
    clocks; flip-flops; timing; clock load; dynamic domino logic; edge-triggered flip-flop; flow-through latch; hybrid latch-flipflop; latency; self-resetting logic; static logic; timing; Aggregates; Circuits; Clocks; Delay; Flip-flops; Frequency; Latches; Logic; Master-slave; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC., 1996 IEEE International
  • Conference_Location
    San Francisco, CA, USA
  • ISSN
    0193-6530
  • Print_ISBN
    0-7803-3136-2
  • Type

    conf

  • DOI
    10.1109/ISSCC.1996.488543
  • Filename
    488543
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3269553