A 6 ns 1.5 V 4 Mb BiCMOS SRAM

Author

Kuhara, S. ; Toyoshima, H. ; Takeda, K. ; Nakamura, K. ; Okamura, H. ; Takada, M. ; Suzuki, H. ; Yoshida, H. ; Yamazaki, T.

Author_Institution

NEC Corp., Kanagawa, Japan

fYear

1996

fDate

10-10 Feb. 1996

Firstpage

144

Lastpage

145

Abstract

Although BiCMOS technology has been used to realize high-speed cache memories, the unscalable 0.8 V Vbe of the bipolar makes it difficult to design 1.5 V BiCMOS circuits including bipolar sense amplifiers. Four circuits in a 0.3 /spl mu/m 4 Mb BiCMOS SRAM overcome this difficulty: (1) boost-BinMOS gates for address decoding, (2) an optimized word-boost for a highly-resistive-load memory cell, (3) a stepped-down CML cascoded bipolar sense amplifier, (4) optimum boost-voltage generator. The SRAM has 6 ns access time at a minimum supply voltage, 1.5 V.

Keywords

BiCMOS memory circuits; SRAM chips; cache storage; 0.3 micron; 1.5 V; 4 Mbit; 6 ns; BiCMOS SRAM; address decoding; boost-BinMOS gates; boost-voltage generator; high-speed cache memory; highly-resistive-load memory cell; stepped-down CML cascoded bipolar sense amplifier; word-boost; BiCMOS integrated circuits; Cache memory; Decoding; Inverters; Leakage current; MOS devices; MOSFETs; National electric code; Random access memory; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC., 1996 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-3136-2

Type

conf

DOI

10.1109/ISSCC.1996.488545

Filename

488545