Title :
A 400 MHz 4.5 Mb synchronous BiCMOS SRAM with alternating bit-line loads
Author :
Suzuki, A. ; Kobayashi, T. ; Hamano, T. ; Hatada, H. ; Kawasumi, A. ; Matsuoka, F. ; Ishimaru, K. ; Takahashi, M. ; Nishigohri, M. ; Okayama, Y. ; Unno, Y. ; Kakumu, M. ; Tsujimoto, J.
Author_Institution :
Semicond. Device Eng. Lab., Toshiba Corp., Kawasaki, Japan
Abstract :
This SRAM explores the feasibility of high-capacity, high-speed off-chip cache memories. The SRAM has a 4.5 Mb capacity with a 128 k/spl times/36 b and 256 k/spl times/18 b configuration. It is fabricated in 0.3 /spl mu/m BiCMOS technology. Alternating bit-line loads and skew-compensated write circuitry with a switched delay decoder are used to raise maximum clock frequency.
Keywords :
BiCMOS memory circuits; SRAM chips; cache storage; 0.3 micron; 4.5 Mbit; 400 MHz; alternating bit-line loads; high-speed off-chip cache memory; skew-compensated write circuitry; switched delay decoder; synchronous BiCMOS SRAM; BiCMOS integrated circuits; Cache memory; Clocks; Decoding; Delay; Pipelines; Random access memory; Registers; Steady-state; Timing;
Conference_Titel :
Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC., 1996 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-3136-2
DOI :
10.1109/ISSCC.1996.488546
