Title :
A 300 MHz, 3.3 V 1 Mb SRAM fabricated in a 0.5 /spl mu/m CMOS process
Author :
Pilo, H. ; Lamphier, S. ; Towler, F. ; Hee, R.
Author_Institution :
Microelectron. Div., IBM Corp., Essex Junction, VT, USA
Abstract :
A 300 MHz, 1 Mb SRAM with 5.4 ns access in 3.3 V, 0.5 /spl mu/m CMOS uses self-timed and self-resetting circuits. A dual-clock, flow-through read protocol optimizes data window control and a 750 ps setup-and-hold window for all input signals is achieved through floorplanning, receiver design and localized input-signal registering. The SRAM interfaces with high-speed transceiver logic (HSTL) levels through high-speed, noise-tolerant receivers. Programmable impedance output drivers for HSTL interfaces match transmission line impedance to within 10% tolerances over process, voltage and temperature variations.
Keywords :
CMOS memory circuits; SRAM chips; 0.5 micron; 1 Mbit; 3.3 V; 300 MHz; 5.4 ns; CMOS SRAM; HSTL interface; data window control; dual-clock flow-through read protocol; floorplanning; high-speed transceiver logic; localized input-signal registering; programmable impedance output driver; receiver design; self-resetting circuits; self-timed circuits; setup-and-hold window; transmission line impedance matching; Access protocols; CMOS logic circuits; CMOS process; Circuit noise; Design optimization; Impedance; Noise level; Random access memory; Signal design; Transceivers;
Conference_Titel :
Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC., 1996 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-3136-2
DOI :
10.1109/ISSCC.1996.488547
