Title :
A 500 MHz 288 kb CMOS SRAM macro for on-chip cache
Author :
Furumochi, K. ; Shimizu, H. ; Fujita, M. ; Akita, T. ; Izawa, T. ; Katsube, M. ; Aoyama, K. ; Kawamura, S.
Author_Institution :
Logic LSI Group, Fujitsu Labs. Ltd., Kanagawa, Japan
Abstract :
A 288 kb (4 kw by 72 b) embedded SRAM macro operates at 500 MHz. A modular design using a double-stage clock generator achieves the word-bit size flexibility required for embedded SRAM. This macro is intended to be used as an on-chip cache for high-speed CPUs.
Keywords :
CMOS memory circuits; SRAM chips; cache storage; macros; 288 kbit; 500 MHz; double-stage clock generator; embedded CMOS SRAM macro; high-speed CPU; modular design; on-chip cache; word-bit size; CMOS logic circuits; CMOS process; Clocks; Driver circuits; Large scale integration; Power supplies; Random access memory; Registers; Timing; Wiring;
Conference_Titel :
Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC., 1996 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-3136-2
DOI :
10.1109/ISSCC.1996.488551
