A 200 MHz 256 kB second level cache with 1.6 GB/s data bandwidth

Author

DiMarco, D. ; Balmer, M. ; Freeman, C. ; Hose, K. ; Miller, J.L. ; Riggs, E.

Author_Institution

Intel Corp., Hillsboro, OR, USA

fYear

1996

fDate

10-10 Feb. 1996

Firstpage

158

Lastpage

159

Abstract

Improvements in processor performance have given rise to tightly-coupled, high-bandwidth second-level caches that are key to processor performance. This paper describes a 256 kB, 4-way set-associative companion cache SRAM to a microprocessor. High speed is achieved by keeping the processor and cache in the same 2-chip module and by communicating over a private 72 b data bus. Supply voltage is 3.3 V and maximum power is 3.8 W at 150 MHz, assuming back-to-back reads. The BiCMOS process features 4-level metal and 0.4 /spl mu/m Leff.

Keywords

BiCMOS memory circuits; SRAM chips; cache storage; content-addressable storage; microprocessor chips; 1.6 GB/s; 200 MHz; 256 kB; 3.3 V; 3.8 W; BiCMOS process; back-to-back reads; data bandwidth; data bus; four-level metal; high speed operation; microprocessor; second level cache; set-associative SRAM; two-chip module; Bandwidth; BiCMOS integrated circuits; Built-in self-test; Clocks; Decoding; Hoses; Microprocessors; Multiplexing; Random access memory; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC., 1996 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-3136-2

Type

conf

DOI

10.1109/ISSCC.1996.488552

Filename

488552