Low-power video encoder/decoder chip set for digital VCRs

Author

Hasegawa, Kiyotomo ; Ohara, Kenichi ; Oka, Akira ; Kamada, Tomonari ; Nagaoka, Yuji ; Yano, Ken´ichi ; Yamauchi, E. ; Kashiro, T. ; Nakagawa, T.

Author_Institution

Semicond. Res. Center, Matsushita Electr. Ind. Co. Ltd., Osaka, Japan

fYear

1996

fDate

10-10 Feb. 1996

Firstpage

164

Lastpage

165

Abstract

Since low-power battery operation is essential for a portable VCR with video camera, the complex computation of MPEG2 encoding is not suitable for consumer digital VCR. This implementation of the video codec using compression optimized for LSI has more than an order of magnitude lower power consumption than that of recently-reported MPEG2 codecs. Power-saving modes and 0.5 /spl mu/m 2 V CMOS standard-cell library also reduce power. Two chips, Shuffling LSI and Compression LSI, together with a 5 Mb DRAM, can either encode the CCIR601 digital component video signal into the standard-definition digital VCR (DVCR) format or decode the DVCR format signal into a component video signal.

Keywords

CMOS digital integrated circuits; digital signal processing chips; large scale integration; video codecs; video signal processing; video tape recorders; 0.5 micron; 2 V; CCIR601 digital signal; CMOS standard-cell; Compression LSI; DRAM; DVCR; Shuffling LS; consumer digital VCR; low-power video codec chip set; portable VCR; Batteries; Decoding; Digital cameras; Encoding; Large scale integration; Portable computers; Transform coding; Video codecs; Video compression; Video recording;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC., 1996 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-3136-2

Type

conf

DOI

10.1109/ISSCC.1996.488554

Filename

488554