The Integration of Multimedia Process Unit into an Embedded Processor

To speed up the processing of the multimedia data, an independent multimedia process unit can be integrated into the embedded processor by SOC technology. Based on one existing embedded processor, the authors design the IP core of the multimedia process unit of the processor. The IP can process two multimedia instructions per cycle. It has six pipeline stages. The complex logic of the dynamic scheduling algorithm is allocated into different stage to alleviate the timing pressure. According to the multimedia benchmarks, the IP core can achieve higher performance with optimal timing and area, so it can improve the whole performance of the embedded processor.