A low-power adiabatic content-addressable memory

This paper presents a novel CAM (content- addressable memory) using CPAL (complementary pass- transistor adiabatic logic) circuits. All circuits except for CAM cells are realized using CPAL circuits. The match-lines are driven using bootstrapped NMOS switches. The charge of large node capacitance on match-lines, bit-lines, word-lines, and address-lines is well recovered in fully adiabatic manner. The power consumption of the proposed CAM is greatly reduced. Simulations show that the proposed CAM attains energy saving of 84% to 92% for search operation compared to the conventional CMOS implementation from 10 MHz to 100 MHz.