A 10 Gb/s BiCMOS clock and data recovering 1:4-demultiplexer in a standard plastic package with external VCO

A test chip for a prototype transmission link performs the task of clock and data recovery together with demultiplexing from 10 to 2.5 Gb/s. The chip uses a BiCMOS process that features a set of devices for high-frequency mixed-signal designs; including 24 GHz NPNs, 0.7 /spl mu/m L/sub eff/ CMOS, 250 and 2000 /spl Omega//sq. polyresistors, 2 fF//spl mu/m/sup 2/ capacitors, Schottky diodes, and lateral PNPs. Early process samples with 16 GHz f/sub T/ are used in the evaluation. Improved performance is expected with the final process. The gates are designed for sufficient speed and nominal VEE of -3.3 V. Even though differential current mode logic (CML) with a differential voltage swing of less than 360 mV/sub pp/ is employed, a wiring capacitance of several 10 fF increases the power-delay product significantly. Wiring length is minimized by local biasing and omission of routing channels. The size of gates with two-level series gating (latch, and, xor) including emitter follower outputs is 67/spl times/58 /spl mu/m/sup 2/. The result of this local biasing scheme is a favourable positive temperature coefficient (TC) for the logic swing, partly compensating for the negative TC of the current switch gain at the cost of high sensitivity to supply variations. All transistors have 0.7 /spl mu/m minimum emitter length, the width avoids the high current region. The other logic gates are downscaled in case of 2.5 GHz operation, input emitter followers omitted in those latches driven from the external clocks.