Delay faults in dual-rail, self-reset wave-pipelined circuits

This paper presents a method to detect delay faults in wave-pipeline high speed arithmetic circuits that are constructed of dual-rail self-reset logic gates with input-disable. For this category of circuits we develop a fault model and show that standard test pattern generation algorithm can be used after using a 9-valued logic set. Also, we demonstrate that as soon as a delay fault occurs at any stage of the pipeline, the fault is eventually manifested at the output of the circuit as if a stuck-at fault existed in the circuit for that wave.